(SVG faylı, nominal olaraq 294 × 587 piksel, faylın ölçüsü: 12 KB)

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İzah
English: The physical layout of a CMOS NAND circuit. The larger regions of N-type diffusion and P-type diffusion are part of the transistors. The two smaller regions on the left are taps to prevent latchup.
עברית: שער לוגי מסוג NAND ממבט על.
Polski: budowa bramki NAND CMOS.
Română: Aranjamentul fizic al unei porţi NAND CMOS.
中文:CMOS与非门的布图.
CMOS NAND Layout for chip
Tarix 7 sentyabr 2006 (original upload date)
Mənbə Transferred from to Commons.
Müəllif Jamesm76 at ingilis Vikipediya
Digər versiyalar Derivative works of this file:  CMOS AND Silicon.svg

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Public domain This work has been released into the public domain by its author, Jamesm76 at ingilis Vikipediya. This applies worldwide.
In some countries this may not be legally possible; if so:
Jamesm76 grants anyone the right to use this work for any purpose, without any conditions, unless such conditions are required by law.

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The original description page was . All following user names refer to en.wikipedia.
  • 2006-09-07 23:46 Jamesm76 294×587×0 (11839 bytes) I am the author and I release this to the public domain.
  • 2006-09-07 23:27 Jamesm76 294×587×0 (11827 bytes) SVG drawing of a CMOS NAND gate replacing the older PNG version I had previously uploaded ("CMOS NAND Layout.png"). I am the author and I release this to the public domain.

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Schematic of CMOS NAND circuit layout

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